1. Field of the Invention
The present invention relates to a transmission front-end processor built in, e.g., an on-board radio apparatus for a nonstop, electronic toll collection (ETC) system applicable to limited-access highways or toll roads. The front-end processor is constructed to modulate a carrier wave with baseband data and radiate the modulated carrier wave.
2. Description of the Background Art
Technologies relating to a transmission front-end processor are disclosed in, e.g., M. D. Pollman et al. "A Low-Cost Package MMIC Chip Set for 5.8 GHz ISM Band Application", 1997 IEEE Radio Frequency Integrated Circuits Symposium (USA), pp. 33-36. A front-end processor taught in this document includes a modulator, a band-pass filter connected to the output of the modulator, and a linear power amplifier connected to the output of the band-pass filter. The power amplifier includes an FET (Field Effect Transistor). Baseband data with a modulation rate of, e.g., 2 Mbaud and a carrier wave Sc lying in a 5.8 GHz band are input to the modulator. The modulator modulates the carrier wave with the baseband data and feeds the resulting signal to the band-pass filter.
More specifically, the modulator controls the amplitude of the carrier wave with the level of the baseband data and outputs an ASK (Amplitude Shift Keying) type of signal. However, the signal output from the modulator contains not only the frequency component of the carrier wave, but also components leaking to adjoining channels due to the frequency components of the baseband data. In light of this, the bandpass filter, or narrow-band channel filter, serves to reduce power leaking to adjoining channels. The maximum power of a signal output from the bandpass filter is not greater than several decibels referred to one milliwatt (dBm) and is smaller than the transmission power required of an ETC system, i.e., 13 dB. The linear power amplifier linearly amplifies the output signal of the bandpass filter so as not to vary the spectrum of the signal and thereby outputs transmission data with power meeting the above requirement.
The above conventional front-end processor has the following problems left unsolved. To provide the signal to be transmitted with the power required of the system, the linear power amplifier including an FET is essential. The FET is designed to perform class-A amplification in order to assure its linearity. However, when the circuitry of the front-end processor is implemented in the form of an IC (Integrated Circuit), the FET is apt to operate at a point deviated from its designed value and therefore in its nonlinear range. This aggravates spurious oscillation and the leakage of power to adjoining channels. The manufacturing of the linear power amplifier in the form of ICs therefore reduces the yield of ICs to a critical degree.
Moreover, to maintain linearity and to send data free from higher order waves or harmonics, the FET of the above linear power amplifier must be so fabricated as to effect power amplification with power up to 1 dB gain compression power (P 1dB). Should the gate width of the FET be increased in order to meet this requirement, the dimensions of the IC chip and therefore the production cost would increase. In addition, because the linear power amplifier must operate at the class-A level, great bias current flows through the amplifier. This is undesirable from the power consumption standpoint.